Integrated circuit design is typically carried out through computer-assisted design instruments, such as “place and route” CAD systems. In such systems, the layouts of the integrated circuits are defined by standard cells which describe the geometric configurations of the masks needed to produce the various arrangements, orientations and interconnections of circuit elements. The group of standard cells available for designing an integrated circuit in accordance with a given manufacturing technology is commonly referred to as a standard cell library. Standard cell libraries typically comprise a fixed set of logic blocks fully characterized for timing, noise, reliability, etc.
Standard cell libraries available commercially are based on boolean logic. This combinational logic is formed primarily from logical “and,” “or” and “invert” functions. Memory elements are typically implemented with flip flops and latches. Normally, the libraries contain a few hundred variations of these fundamental cells. Higher level logic, including arithmetic blocks such as adders and multipliers, is constructed from combinations of these standard cells.
Designers commonly employ standard cell libraries due to the robustness and flexibility of the libraries. This saves time and money by reducing product development cycle time. Additionally, risk is reduced by using predesigned, pretested and precharacterized standard cell libraries.
However, an integrated circuit designed with standard cells often results in an undesirable signal skew. For example, an ideal signal waveform may have a 50/50 or 50% duty cycle, where the amount of time the signal is high is equal to the amount of time the signal is low in a given period. Signal skew, also referred to herein as duty cycle distortion, occurs when the amount of time the signal is high is substantially larger or smaller than the amount of time the signal is low in a given period of the waveform. For example, an ideal waveform having a period of 10 ns (nanoseconds) may have a 5 ns-high/5 ns-low pattern, while a waveform that is skewed may have a 6 ns-high/4 ns-low pattern, resulting in a signal skew of 2 ns.
Previous attempts to solve this problem involved making customized cells, hand-modifying existing standard cells, and utilizing manual place and route modifications to tune a given circuit. U.S. Pat. Nos. 6,690,202 and 6,507,220 describe circuitry for correcting or preventing duty cycle distortion through equating signal voltage to a logic threshold voltage of the integrated circuit. U.S. Pat. No. 6,411,145 describes a circuit configured to correct a duty cycle through differential pairs of transistors configured to change a DC level of the inputs of the integrated circuit. U.S. Pat. No. 5,757,218 describes a duty cycle correction circuit having a comparator circuit and a control circuit. JP Patent Publication Nos. 2003-152078 and 08-077227 describe the use of RC effects in changing the total delay of a cell.
These techniques force the integrated circuit designer to depart from the standard design flow methods used in standard cell integrated circuit designs. The requirement of manually customizing cells or modifying the circuit layout can lengthen and complicate design cycle times, possibly adding extra risk, cost and schedule delay. Thus, a need remains for further improvements in signal skew adjustment in digital circuitry of an integrated circuit.